1. Field of the Invention
This invention relates to output buffer circuits. Specifically, the invention relates to tristate buffer circuits for use in mixed voltage applications, where a design requires that a circuit using one supply voltage be able to drive a circuit with a higher supply voltage.
2. Prior Art
Low voltage components are becoming more popular in many card designs because of their lower power consumption and high performance. These low voltage components are typically 3.3 Volt CMOS components, and are integrated onto a single integrated circuit chip. However, often it is desirable to design a system in which a low voltage chip is required to drive readily available, low cost higher supply voltage components. These older chips are typically designed to operate with a 5 Volt power supply as opposed to the 3.3 Volt power supply required to power low voltage CMOS.
A conventional output buffer for a low power 3.3 Volt CMOS integrated circuit chip is shown in FIG. 5. This design includes a standard pull-up, pull-down transistor arrangement which is well-known and used in many buffer circuits. T1 is a normally-off p-channel field effect transistor used as a pull-up transistor, and T0 is a normally-off n-channel field effect transistor used as a pull-down transistor.
Problems occur when a 3.3 volt chip having a buffer circuit like that shown in FIG. 5 is connected to higher voltage components, for example, a 5 volt peripheral transceiver chip. These problems include gate oxide breakdown, hot electron effects, and undesirable reverse leakage currents caused by P/N junctions becoming unintentionally forward biased due to the higher voltage present at the driver output when the 5 Volt transceiver chip input/output is high. All of these problems are well understood in the art. Gate oxide and maximum drain-source voltage protection are commonly achieved with the addition of a series n-channel field effect transistor to the conventional buffer circuit. The reverse leakage problem is discussed below.
One solution to the undesirable leakage current problem requires a depletion device be connected between the output pad and the pull-up PFET. This device prevents the P/N junctions of the PFET from becoming forward biased as the output rises above the 3.3 Volt supply voltage. This solution is described in the publication, Highly Reliable Process Insensitive 3.3V-5V Interface Circuit, Y. Wada, J. Gotoh, H. Takakura, T. Iida, and T. Noguchi, Toshiba Semiconductor System Engineering Center, June 1992, which is incorporated herein by reference. Unfortunately, most practical, automated CMOS manufacturing processes do not offer a depletion device.
Another solution involves the use of a "floating n-well" technique. With this technique, a small contention p-channel field effect transistor (PFET) is connected between the gate of the pull-up transistor and the output pad of the circuit. When the driver is tristated and the output is driven above the chip supply voltage (Vdd) by the 5 Volt peripheral, the floating N-well of the pull-up transistor will rise to within a diode drop of the output voltage level. Simultaneously, the contention PFET will pull the gate of the pull-up transistor to the voltage level of the output pad. Both of these actions together stop the reverse flow of current through the buffer circuit into the chip power supply. The floating n-well technique is further described in the article, "A 3.3V ASIC for Mixed Voltage Applications with Shutdown Mode", Proceedings of the IEEE Customer Integrated Circuits Conference, M. Ueda et. al., May 1992, which is incorporated herein by reference.
One shortcoming of the above approach is that the contention PFET device is biased at chip Vdd and can not turn off the pull-up PFET unless the pull-up current on the 5 Volt chip's bidirectional output buffer can override the current sink capability of the pull-up PFET. Another problem occurs during active mode when a pull-up resistor connected to the 3.3 Volt chip's output pad is terminated to 5 volts. In practice, the termination can be made directly to the 5 volt supply on a mixed voltage circuit card or inside the 5 Volt peripheral chip. When the output pad of the buffer circuit is driven high, the gate of the pull-up transistor is at ground and can never be pulled up to 5 Volts by the contention device. The output of the buffer circuit will always be clamped to Vdd when the output is high, thus allowing reverse current to flow through the pull-up resistor into the chip 3.3 Volt power supply. This situation is illustrated in FIG. 6. The reverse current is labeled Ir. What is needed is a floating n-well design that eliminates leakage current in both the active and tristate modes.